`timescale 1ns / 1ps 
//////////////////////////////////////////////////////////////////////////////////
// Company:     Fraser Innavotion Inc
// Engineer:    Qianqi(Tim) Zhuang & William Gou
//
// Create Date: 09/25/2018 09:28:18 AM
// Modified Date: 2020-02-28
// Design Name:
// Module Name: csr_mcounteren
// Project Name: RISC-V SOC RTL
// Target Devices: FII-PE7030, FII-PRX100T, FII-BM7100, FII-PRA040, FII-PRA006
// Tool Versions: vivado 18.1/18.2
// Description:
//
// Dependencies:
// this is a simple version of risc-v integer version,aim to show up basic concept of RTL
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module csr_mcounteren
(
    input sys_clk,

    input [ 11: 0 ] i_csr_addr,
    input [ 31: 0 ] i_csr_val,
    input i_csr_wen,

    output [ 31: 0 ] o_mcounteren,

    input rst_n
);


wire mcounteren_ena =  (i_csr_wen & (i_csr_addr == 12'h306));
wire [31:0] mcounteren_r;
wire [31:0] mcounteren_nxt = i_csr_val;

yue_dfflr #(32) mtvec_dfflr (mcounteren_ena, mcounteren_nxt, mcounteren_r, sys_clk, rst_n);

assign          o_mcounteren = mcounteren_r;




endmodule
